Apparatus and method for controlling controllable clock source to generate clock signal with frequency transition

ABSTRACT

A clock generator includes a controllable clock source and a frequency hopping controller. The controllable clock source generates a clock signal to a clock-driven device. The frequency hopping controller controls the controllable clock source to make the clock signal have at least one frequency transition from one clock frequency to another clock frequency, wherein the controllable clock source stays in a frequency-locked state during a time period of the at least one frequency transition.

CROSS REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of U.S. provisional application No.61/858,742, filed on Jul. 26, 2013 and incorporated herein by reference.

BACKGROUND

The disclosed embodiments of the present invention relate to changing aclock frequency of a clock signal used by a clock-driven device, andmore particularly, to an apparatus and method for controlling acontrollable clock source to generate a clock signal with a frequencytransition under a condition that the controllable clock source stays ina frequency-locked state.

A memory device is a key component of an electronic device. For example,the memory device may include a dynamic random access memory (DRAM) usedto buffer instructions and data. The computational workload of theelectronic device is not always high. If the memory device is operatedat a highest clock frequency under a normal mode, this would result inhigher power consumption. The conventional power management design maychange the clock frequency of the memory clock when the computationalworkload of the electronic device is lower than a threshold. The reducedclock frequency also enables the supply voltage to be reduced, whichdecreases power consumption and extends battery life (if the electronicdevice is a portable device powered by a battery).

In general, the memory clock is generated from a clock generator, suchas a phase-locked loop (PLL). When the clock frequency of the memorydevice is allowed to be reduced, the memory controller controls thememory device to enter a self-refresh mode, and then adjusts the PLL soas to change the clock frequency of the memory clock. However, when aninput of the PLL has a significant frequency change, the memory clockgenerated from the clock generator may fail to swiftly track thefrequency variation of the PLL input. Thus, the PLL leaves afrequency-locked state. The generation of the memory clock is not stableuntil the PLL enters the frequency-locked state again. However, the PLLneeds a period of time to enter the frequency-locked state again toprovide a stable memory clock with the reduced clock frequency. As aresult, the system is unable to access the memory device before the PLLprovides a stable memory clock with the reduced clock frequency and thememory device leaves the self-refresh mode. If there is a real-time taskthat needs to access the memory device at a moment that access of thememory device is unavailable due to frequency change, the real-time taskfails to work normally, which may lead to system malfunction.

SUMMARY

In accordance with exemplary embodiments of the present invention, anapparatus and method for controlling a controllable clock source togenerate a clock signal with a frequency transition under a conditionthat the controllable clock source stays in a frequency-locked state areproposed to solve the above-mentioned problem.

According to a first aspect of the present invention, an exemplary clockgenerator is provided. The exemplary clock generator includes acontrollable clock source and a frequency hopping controller. Thecontrollable clock source is configured to generate a clock signal to aclock-driven device. The frequency hopping controller is configured tocontrol the controllable clock source to make the clock signal have atleast one frequency transition from one clock frequency to another clockfrequency, wherein the controllable clock source stays in afrequency-locked state during a time period of the at least onefrequency transition.

According to a second aspect of the present invention, an exemplaryclock generating method is provided. The exemplary clock generatingmethod includes: utilizing a controllable clock source to generate aclock signal to a clock-driven device; and controlling the controllableclock source to make the clock signal have at least one frequencytransition from one clock frequency to another clock frequency, whereinthe at least one frequency transition is controlled to prevent thecontrollable clock source from leaving a frequency-locked state during atime period of the at least one frequency transition.

According to a third aspect of the present invention, an exemplaryelectronic device is provided. The exemplary electronic device includesa memory controller and a processor. The memory controller is configuredto control access of a memory device. The processor is configured toperform a calibration operation to find a first setting range of amemory controller parameter under a first clock frequency of the memorydevice, find a second setting range of the memory controller parameterunder a second clock frequency of the memory device, and determine acalibrated setting of the memory controller parameter according to anoverlapped range of the first setting range and the second settingrange.

According to a fourth aspect of the present invention, an exemplaryelectronic device is disclosed. The exemplary electronic device includesa processor and a clock generator. The processor is configured toperform a calibration operation to find a skew value between a datastrobe (DQS) signal and a clock signal of a memory device. The clockgenerator has a controllable clock source and a frequency hoppingcontroller. The controllable clock source is configured to generate theclock signal to the memory device. The frequency hopping controller isconfigured to control frequency hopping of the controllable clock sourceaccording to the skew value.

These and other objectives of the present invention will no doubt becomeobvious to those of ordinary skill in the art after reading thefollowing detailed description of the preferred embodiment that isillustrated in the various figures and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram illustrating an electronic device according toan embodiment of the present invention.

FIG. 2 is a diagram illustrating dynamic frequency scaling withfrequency hopping controlled by the frequency hopping controller shownin FIG. 1.

FIG. 3 is a diagram illustrating spread spectrum clocking with frequencyhopping controlled by the frequency hopping controller shown in FIG. 1.

FIG. 4 is a flowchart illustrating a boot-time calibration operationaccording to an embodiment of the present invention.

DETAILED DESCRIPTION

Certain terms are used throughout the description and following claimsto refer to particular components. As one skilled in the art willappreciate, manufacturers may refer to a component by different names.This document does not intend to distinguish between components thatdiffer in name but not function. In the following description and in theclaims, the terms “include” and “comprise” are used in an open-endedfashion, and thus should be interpreted to mean “include, but notlimited to . . . ”. Also, the term “couple” is intended to mean eitheran indirect or direct electrical connection. Accordingly, if one deviceis coupled to another device, that connection may be through a directelectrical connection, or through an indirect electrical connection viaother devices and connections.

The key idea is to make a memory device (e.g., DRAM or any other memorydevice driven by a clock) still accessible to a system when a clockgenerator is changing a clock frequency of the memory device. Forexample, a frequency hopping scheme may be employed by the clockgenerator to generate a clock signal having a piecewise/smooth frequencytransition. As the frequency hopping scheme can prevent the clockgenerator from leaving a frequency-locked state, the clock generator iscapable of outputting a frequency-locked clock signal. In addition, theinternal clock circuitry of the memory device is able to track thefrequency variation of the clock signal generated from the clockgenerator, such that the memory device can work normally during thefrequency change period. In this way, the real-time tasks would worknormally during the procedure of changing the clock frequency of thememory clock. Preferably, the reduced clock frequency may also enablethe supply voltage to be reduced, which achieves better power savingperformance. Further details of technical features of the presentinvention are described as below.

FIG. 1 is a block diagram illustrating an electronic device according toan embodiment of the present invention. By way of example, but notlimitation, the electronic device 100 may be a mobile phone using theproposed frequency hopping scheme to change a memory clock frequency forpower saving. The electronic device 100 can also be a tablet, wearabledevice, notebook or any other electronic device having or being coupledto a memory device. As shown in FIG. 1, the electronic device 100 mayinclude a processor 102, a memory controller 104 and a memory device(e.g. , DRAM or any other memory device driven by a clock) 106. Thememory controller 104 may include a control core 107 and a clockgenerator 108. The memory controller 104 may be configured to controlaccess (i.e., read and write) of the memory device 106. Hence, theprocessor 102 may issue a read request to the memory controller 104 forreading stored data from a read address of the memory device 106, andissue a write request to the memory controller 104 for writing inputdata to a write address of the memory device 106. It should be notedthat FIG. 1 only shows circuit components pertinent to technicalfeatures of the present invention. In practice, the electronic device100 may include additional circuit components to achieve its designatedfunctionality.

The control core 107 of the memory controller 104 may be responsible forserving read requests and write requests issued from other circuitcomponents (e.g., processor 102) in the electronic device 100.Specifically, the control core 107 may communicate with the memorydevice 106 via data signals, address and command signals and controlsignals. For example, the data signals may include a data strobe (DQS)signal, a data strobe complement (DQS#) signal, a data (DQ) signal, etc.The address and command signals may include a bank address (BA) signal,an address (ADDR) signal, and command inputs such as a row addressstrobe (RAS) signal, a column address strobe (CAS) signal, a writeenable (WE) signal, etc. The control signals may include a clock enable(CKE) signal, a chip select (CS) signal, an on-die termination (ODT)signal, etc. As a person skilled in the art should readily understanddetails of above-mentioned signals, further description is omitted herefor brevity.

The memory device 106 may be a clock-driven device, and thus requires aclock signal CK to perform its designated functionality. In thisembodiment, the clock generator 108 may include a frequency hoppingcontroller 112 and a controllable clock source 114. The frequencyhopping controller 112 is shown as part of the memory controller 104.However, this is not meant to be a limitation of the present invention.Alternatively, the frequency hopping controller 112 maybe implemented ina different circuit block, such as a baseband (BB) chip. That is, thefrequency hopping controller 112 may be an external component of thememory controller 104. Hence, the clock generator 108 proposed by thepresent invention may be configured to include an internal component ofthe memory controller 104 (e.g., controllable clock source 114) and anexternal component of the memory controller 104 (e.g., frequency hoppingcontroller 112). This alternative design also falls within the scope ofthe present invention. In the following, technical features of theproposed clock generator 108 are detailed based on the exemplaryarchitecture shown in FIG. 1.

The controllable clock source 114 maybe configured to generate the clocksignal CK to the memory device 106. For example, the controllable clocksource 114 maybe implemented using a phase-locked loop (PLL) which actsas a frequency synthesizer. The frequency hopping controller 112 maybecoupled to the controllable clock source 114, and may be configured tocontrol the controllable clock source 114 to set the clock frequency ofthe clock signal CK. When the computational workload of the electronicdevice 100 is low, the clock signal CK may be controlled to have areduced clock frequency for power saving. In this case, the frequencyhopping controller 112 may be operative to make the clock signal CK haveat least one frequency transition from one clock frequency (e.g., ahighest clock frequency supported by the memory device 106) to anotherclock frequency (e.g., a lower clock frequency supported by the memorydevice 106), wherein the controllable clock source 114 stays in afrequency-locked state during a time period of the at least onefrequency transition. As the frequency hopping controller 112 canprevent the controllable clock source 114 from leaving thefrequency-locked state, the controllable clock source 114 does not needto spend additional time on re-entering the frequency-locked state togenerate a frequency-locked clock.

In one exemplary frequency hopping design, the frequency hoppingcontroller 112 maybe configured to employ dynamic frequency scaling(DFS) to control a frequency transition of the clock signal CK. FIG. 2is a diagram illustrating DFS with frequency hopping controlled by thefrequency hopping controller 112 shown in FIG. 1. The frequencytransition from a current clock frequency F_(cur) to a target clockfrequency F_(tar) may be a smooth frequency transition as represented bythe characteristic curve CV1 with a constant slope. To speedup thefrequency transition from the current clock frequency F_(cur) to thetarget clock frequency F_(tar), the clock signal CK may be controlled byDFS to have a piecewise frequency transition as represented by thecharacteristic curve CV2 with different slopes. In this example, theabsolute value of the initial slope is set by a large value to quicklychange the clock frequency in a short time, thus shortening theprocessing time needed for changing the clock frequency from F_(cur), toF_(tar). It should be noted that the initial slope should be properlycontrolled to keep the controllable clock source 114 still staying inthe frequency-locked state. Next, the absolute value of the slope isgradually reduced to make the clock frequency approach F_(tar) withoutundesired overshoot. During a period in which the clock frequencychanges with time, the frequency hopping controller 112 can prevent theclock frequency from having a sudden frequency jump that exceeds afrequency variation threshold, thereby keeping the controllable clocksource 114 staying in the frequency-locked state.

It should be noted that any of the smooth frequency transition or thepiecewise frequency transition should be properly controlled to ensurethat the controllable clock source 108 stays in the frequency-lockedstate. FIG. 2 illustrates a smooth/piecewise frequency transition from alow clock frequency to a high clock frequency. However, the sameDFS-based frequency hopping concept may be employed by the frequencyhopping controller 112 to make the clock signal CK have asmooth/piecewise frequency transition from a high clock frequency to alow clock frequency. Further description is omitted here for brevity.

In another exemplary frequency hopping design, the frequency hoppingcontroller 112 may be configured to employ spread spectrum clocking(SSC) to control consecutive frequency transitions of the clock signalCK. FIG. 3 is a diagram illustrating SSC with frequency hoppingcontrolled by the frequency hopping controller 112 shown in FIG. 1. Thefrequency hopping controller 112 may apply a free-run mode control tothe controller clock source 114, such that the clock signal CK changesits clock frequency back and forth between a first clock frequency F₁and a second clock frequency F₂. In other words, the clock frequency ofthe clock signal CK gradually moves from the first clock frequency F₁ tothe second clock frequency F₂ and gradually moves from the second clockfrequency F₂ to the first clock frequency F₁, alternatively. In thisembodiment, the second clock frequency F₂ is the highest clock frequencysupported by the memory device 106, and the first clock frequency F₁ isgenerated by modulating the second clock frequency F₂ based on atriangle waveform. For example, when the SSC amplitude is set by 8%,F₁=(1-8%)*F₂.

In a first scenario, the frequency hopping controller 112 may controlthe controllable clock source 114 to make the clock signal CK have afrequency transition when a clock enable (CKE) control signal of thememory device 106 is asserted (i.e., CKE=1). Thus, the DFS/SSCprocessing of the clock signal CK is performed in the background so thememory device 106 can still be accessed at run-time. As the frequencyhopping controller 112 prevents the controllable clock source 114 fromleaving the frequency-locked state, the clock frequency of the clocksignal CK does not have a significant frequency change, thus allowingthe internal clock circuitry of the memory device 106 to swiftly trackthe frequency variation of the clock signal CK. In this way, the memorydevice 106 can still operate normally during the frequency changeperiod. For example, the memory device 106 may be a DRAM, and the clocksignal CK may be controlled to have a frequency transition from 1600 MHzto 1066 MHz for power saving.

Further, the memory controller 104 may use the same set of memory timingparameters when the clock signal CK of the memory device 106 has atransition from one clock frequency to another clock frequency. In oneexemplary design, a boot-time calibration operation may be performed bythe processor 102 to calibrate at least one memory controller parameterwhen the electronic device 100 is booted up, and a run-time trackingoperation may be performed by the memory controller 104 to dynamicallyadjust the at least one memory controller parameter when the clockfrequency of the clock signal CK is being adjusted by the proposedfrequency hopping scheme. For example, the memory controller parameterschecked by the boot-time calibration operation may include a data strobe(DQS) gating window and a data latch (DATLAT) time. In addition, theboot-time calibration operation may further check inherentcharacteristics of the memory device 106, such as a skew value t_(DQSCK)between the data strobe (DQS) signal and the clock signal CK of thememory device 106.

FIG. 4 is a flowchart illustrating a boot-time calibration operationaccording to an embodiment of the present invention. Provided that theresult is substantially the same, the steps are not required to beexecuted in the exact order shown in FIG. 4. Besides, one or more stepsmay be omitted according to different embodiments of this invention. Forexample, a portion or all of steps 406, 410 and 414 maybe omitted insome embodiments. The boot-time calibration operation maybe performed bythe processor 102 running program codes of a calibration softwaremodule, and may be briefly summarized as below.

Step 402: The electronic device 100 is booted up.

Step 404: Find a first setting range of the DQS gating window under afirst clock frequency of the memory device 106. For example, the firstclock frequency is a lowest clock frequency of a frequency transition ofthe clock signal CK, or a clock frequency lower than a nominal clockfrequency of the memory device 106.

Step 406: Find a first setting range of the DATLAT time under the firstclock frequency of the memory device 106.

Step 408: Find a second setting range of the DQS gating window under asecond clock frequency of the memory device 106. For example, the secondclock frequency is a highest clock frequency of the frequency transitionof the clock signal CK, or a highest clock frequency (i.e., a nominalclock frequency) supported by the memory device 106.

Step 410: Find a second setting range of the DATLAT time under thesecond clock frequency of the memory device 106.

Step 412: Determine a calibrated setting of the DQS gating windowaccording to an overlapped range of the first setting range of the DQSgating window and the second setting range of the DQS gating window.

Step 414: Determine a calibrated setting of the DATLAT time according toan overlapped range of the first setting range of the DATLAT time andthe second setting range of the DATLAT time.

Step 416: Find the skew value t^(DQSCK) between the data strobe (DQS)signal and the clock signal CK of the memory device 106. For example,the skew value t_(DQSCK) may be evaluated under the second clockfrequency of the memory device 106.

In step 412, an overlapped range of the first setting range of the DQSgating window and the second setting range of the DQS gating window maybe checked to fine tune the setting of the DQS gating window. In thisway, the calibrated setting of the DQS gating window is capable ofmeeting the requirement of eliminating signal noise and/or undesirablesignal regions of the DQS signal generated under any of the first clockfrequency and the second clock frequency.

In step 414, an overlapped range of the first setting range of theDATLAT time and the second setting range of the DATLAT time is checkedto fine tune the setting of the DATLAT time. In this way, the calibratedsetting of the DATLAT time is capable of meeting the read data marginrequirement of holding the read data coming from the memory device 106due to a read operation performed under any of the first clock frequencyand the second clock frequency.

After the boot-time calibration operation is completed, the electronicdevice 100 may enter a normal mode to perform its designatedfunctionality. Initially, the memory controller 104 may be configuredbased on the boot-time calibration result, and may generate the clocksignal CK with the nominal clock frequency of the memory device 106(i.e., the highest clock frequency supported by the memory device 106).When a condition of reducing the memory clock frequency is met, thefrequency hopping controller 112 may control the controllable clocksource 114 to make the clock signal CK have the transition from thehighest clock frequency supported by the memory device 106 to a lowerclock frequency supported by the memory device 106. Further, a run-timetracking mechanism is activated to dynamically adjust the memorycontroller parameters (e.g., DQS gating window and/or DATLAT time)during the time period of the frequency transition. This may enable thememory device 106 to be correctly accessed in different clockfrequencies.

The skew value t_(DQSCK) between the DQS signal and the clock signal CKof the memory device 106 may be referenced by the frequency hoppingcontroller 112 to control frequency hopping of the controllable clocksource 114. In one embodiment, the frequency transition from one clockfrequency to another clock frequency may be set based on the skew valuet_(DQSCK). For example, when the skew value t_(DQSCK) has a smallervalue, the clock signal CK may be allowed to have a larger frequencytransition from 1600 MHz to 1066 MHz; and when the skew value t_(DQSCK)has a larger value, the clock signal CK may only be allowed to have asmaller frequency transition from 1600 MHz to 1466 MHz. In other words,the skew value t_(DQSCK) may be referenced by the frequency hoppingcontroller 112 to decide the frequency transition range, such that thememory device 106 can still work normally when the memory clockfrequency is adjusted.

In a worst case where the skew value t_(DQSCK) is larger than apredetermined threshold, the frequency hopping function may be disabled.For example, the frequency hopping controller 112 may be furtherconfigured to compare the skew value t_(DQSCK) with the predeterminedthreshold, and disable the frequency hopping of the controllable clocksource 114 when a comparison result indicates that the skew valuet_(DQSCK) is larger than the predetermined threshold.

In above embodiments, frequency hopping of the controllable clock source114 is active when the clock enable (CKE) control signal of the memorydevice 106 is asserted (i.e., CKE=1). Further, the frequency hopping ofthe controllable clock source 114 may be active when the low-active chipselect (CS) signal is asserted (i.e., CS=0).

The memory device 106 is allowed to be accessed during the frequencychange period. If there is a real-time task that needs to access thememory device 106 at this moment, the real-time task can work normally.However, this is for illustrative purposes only, and is not meant to bea limitation of the present invention. In an alternative design, thefrequency hopping controller 112 may control the controllable clocksource 114 to make the clock signal CK have a frequency transition whenthe clock enable (CKE) control signal of the memory device 106 isde-asserted (i.e., CKE=0). This also falls within the scope of thepresent invention.

In above embodiments, the clock generator 108 is implemented in theelectronic device 100 to provide the clock signal CK to the memorydevice (e.g. , DRAM or any other memory device driven by a clock) 106.However, this is not meant to be a limitation of the present invention.Any electronic device using the proposed clock generator 108 to providea clock signal to a clock-driven device falls within the scope of thepresent invention.

Those skilled in the art will readily observe that numerousmodifications and alterations of the device and method may be made whileretaining the teachings of the invention. Accordingly, the abovedisclosure should be construed as limited only by the metes and boundsof the appended claims.

What is claimed is:
 1. A clock generator, comprising: a controllableclock source, configured to generate a clock signal to a clock-drivendevice; and a frequency hopping controller, configured to control thecontrollable clock source to make the clock signal have at least onefrequency transition from one clock frequency to another clockfrequency, wherein the controllable clock source stays in afrequency-locked state during a time period of the at least onefrequency transition.
 2. The clock generator of claim 1, wherein theclock-driven device is a memory device.
 3. The clock generator of claim2, wherein the frequency hopping controller controls the controllableclock source to make the clock signal have the at least one frequencytransition when a clock enable (CKE) control signal of the memory deviceis asserted.
 4. The clock generator of claim 2, wherein the frequencyhopping controller controls the controllable clock source to make theclock signal have the at least one frequency transition when a clockenable (CKE) control signal of the memory device is de-asserted.
 5. Theclock generator of claim 1, wherein the frequency hopping controller isconfigured to employ dynamic frequency scaling (DFS) to control the atleast one frequency transition of the clock signal.
 6. The clockgenerator of claim 1, wherein the frequency hopping controller isconfigured to employ spread spectrum clocking (SSC) to control the atleast one frequency transition of the clock signal.
 7. A clockgenerating method, comprising: utilizing a controllable clock source togenerate a clock signal to a clock-driven device; and controlling thecontrollable clock source to make the clock signal have at least onefrequency transition from one clock frequency to another clockfrequency, wherein the at least one frequency transition is controlledto prevent the controllable clock source from leaving a frequency-lockedstate during a time period of the at least one frequency transition. 8.The clock generating method of claim 7, wherein the clock-driven deviceis a memory device.
 9. The clock generating method of claim 8, whereinthe step of controlling the controllable clock source to make the clocksignal have the at least one frequency transition is performed when aclock enable (CKE) control signal of the memory device is asserted. 10.The clock generating method of claim 8, wherein the step of controllingthe controllable clock source to make the clock signal have the at leastone frequency transition is performed when a clock enable (CKE) controlsignal of the memory device is de-asserted.
 11. The clock generatingmethod of claim 7, wherein the step of controlling the controllableclock source to make the clock signal have the at least one frequencytransition comprises: employing dynamic frequency scaling (DFS) tocontrol the at least one frequency transition of the clock signal. 12.The clock generating method of claim 7, wherein the step of controllingthe controllable clock source to make the clock signal have the at leastone frequency transition comprises: employing spread spectrum clocking(SSC) to control the at least one frequency transition of the clocksignal.
 13. An electronic device, comprising: a memory controller,configured to control access of a memory device; and a processor,configured to perform a calibration operation to find a first settingrange of a memory controller parameter under a first clock frequency ofthe memory device, find a second setting range of the memory controllerparameter under a second clock frequency of the memory device, anddetermine a calibrated setting of the memory controller parameteraccording to an overlapped range of the first setting range and thesecond setting range.
 14. The electronic device of claim 13, wherein thememory controller parameter is a data strobe (DQS) gating window. 15.The electronic device of claim 13, wherein the memory controllerparameter is a data latch (DATLAT) time.
 16. An electronic device,comprising: a processor, configured to perform a calibration operationto find a skew value between a data strobe (DQS) signal and a clocksignal of a memory device; and a clock generator, comprising: acontrollable clock source, configured to generate the clock signal tothe memory device; and a frequency hopping controller, configured tocontrol frequency hopping of the controllable clock source according tothe skew value.
 17. The electronic device of claim 16, wherein thefrequency hopping controller is configured to set a frequency transitionfrom one clock frequency to another clock frequency according to theskew value, and control the controllable clock source to make the clocksignal have the frequency transition.
 18. The electronic device of claim17, wherein the frequency hopping controller is configured to employdynamic frequency scaling (DFS) to control the frequency transition ofthe clock signal.
 19. The electronic device of claim 17, wherein thefrequency hopping controller is configured to employ spread spectrumclocking (SSC) to control the frequency transition of the clock signal.20. The electronic device of claim 16, wherein the frequency hoppingcontroller is configured to compare the skew value with a predeterminedthreshold, and disable the frequency hopping of the controllable clocksource when a comparison result indicates that the skew value is largerthan the predetermined threshold.